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AArch64 W+W+WR+pospteafp-[dsb.ish]-[isb]+PteOAPteAF
"CoePteOAPteAF CoePteAFPteAF PosWRPteAFP DSB.ISH ISB FrePPteOA"
variant=precise
Cycle=ISB FrePPteOA CoePteOAPteAF CoePteAFPteAF PosWRPteAFP DSB.ISH
Relax=PteAF PteOA
Safe=Fre Coe [PosWR,DSB.ISH,ISB]
Generator=diy7 (version 7.56+02~dev)
Com=Co Co Fr
Orig=CoePteOAPteAF CoePteAFPteAF PosWRPteAFP DSB.ISH ISB FrePPteOA
{
pteval_t 1:X2; pteval_t 0:X2;
int x=0; int y=4;
0:X0=PTE(x); 0:X1=(oa:PA(y));
1:X0=PTE(x); 1:X1=(oa:PA(y), af:0);
2:X0=PTE(x); 2:X1=(oa:PA(y)); 2:X2=x;
}
P0 | P1 | P2 ;
STR X1,[X0] | STR X1,[X0] | STR X1,[X0] ;
LDR X2,[X0] | LDR X2,[X0] | DSB ISH ;
| | ISB ;
| | LDR W3,[X2] ;
exists (0:X2=(oa:PA(y)) /\ 1:X2=(oa:PA(y)) /\ 2:X3=0 /\ fault(P2,x,MMU:AccessFlag)) \/ (0:X2=(oa:PA(y), af:0) /\ 1:X2=(oa:PA(y)) /\ 2:X3=4 /\ ~fault(P2,x)) \/ (0:X2=(oa:PA(y), af:0) /\ 1:X2=(oa:PA(y), af:0) /\ 2:X3=0 /\ fault(P2,x,MMU:AccessFlag))